1. Field of the Invention
The present invention relates to an electrical and thermal contact for use in semiconductor devices. Particularly, the present invention relates to an electrical and thermal contact which reduces the amount of energy input that is required in order to switch a semiconductor device structure that is contacted thereto between two or more states. More specifically, the electrical and thermal contact of the present invention includes thin conductive layers which envelop an insulator component. The electrical and thermal contact is particularly useful for switching contacted structures that include a phase change component between two or more states of electrical conductivity.
2. State of the Art
Electrically erasable programmable memory devices (EEPROMS) typically include several memory elements that may be switched between a first logic state and a second logic state. A first logic state may be an inactive state, or an xe2x80x9coffxe2x80x9d state, wherein electrical impulses do not travel across the memory element. Memory elements may be said to be in a second logic state, such as an xe2x80x9cactivatedxe2x80x9d state or an xe2x80x9conxe2x80x9d state, when low voltage electrical impulses (i.e., of the operational voltage of the EEPROM) will readily travel thereacross.
Memory elements may comprise fuse elements or antifuse elements. Fuse elements are programmed by xe2x80x9cblowingxe2x80x9d (i.e., breaking the electrical connection across) the fuse thereof, which switches the fuse elements from an active state to an inactive state. Conversely, antifuse elements are programmed by forming a low resistance electrical path across (i.e., activating) the antifuses thereof. The programming of both fuse and antifuse elements requires the application of a sufficient current and voltage to such memory elements. Nevertheless, the application of too great a current to memory elements, such as fuse and antifuse elements, increases the potential that various other components of the EEPROM of which they are a part, including without limitation the gate oxide layer, transistors, and other structures on the surface thereof, may be damaged.
FIG. 1 is a schematic representation of an exemplary conventional antifuse element 1, which includes a metal contact 2, first and second electrodes 4 and 8, respectively, and a dielectric layer 6, which electrically insulates the first electrode 4 from the second electrode 8. Metal contact 2 is typically a large element relative to the remainder of antifuse element 1. As a current is applied to metal contact 2, the resistance that is generated thereby and by at least one of the electrodes 4, 8 that are in contact therewith locally heats dielectric layer 6, destroying at least a portion of the same and facilitating the formation of an electrically conductive pathway between first electrode 4 and second electrode 8. Thus, an electrical contact is established between first and second electrodes 4 and 8, respectively, thereby activating the antifuse element.
As noted previously, programming pulses which comprise high electrical voltages may damage various components of an EEPROM, including, without limitation, the gate oxide layer, transistors and other structures on the surface of the EEPROM. Consequently, in order to reduce the potential for damaging EEPROMs during the programming thereof, the programming pulses for EEPROMs are ever-decreasing, as are the normal operating voltages thereof. State of the art EEPROMs typically operate at either 5V or 3.3V. U.S. Pat. No. 5,486,707, issued to Kevin T. Look et al. on Jan. 23, 1996, discloses an exemplary programmable memory that includes antifuse elements that may be switched to an xe2x80x9conxe2x80x9d state by a programming voltage of about 7.5V to about 10V. While in the xe2x80x9coffxe2x80x9d state, the electrical resistance of a typical EEPROM antifuse element is on the order of about 1 gigaohm or greater. After an antifuse of a typical state of the art EEPROM has been switched to the xe2x80x9conxe2x80x9d state by a programming pulse, the former has a low electrical resistance, on the order of tens of ohms or less.
The memory elements of such state of the art EEPROMs typically have lower programming voltage requirements than their predecessors, due to the structure of the memory elements of the former and the materials that are utilized in the memory elements. While the programming voltage requirements of such EEPROMs are ever-decreasing, due to the widespread use of conventional, low thermal impedance metal contacts in connection with the antifuse elements thereof, an extremely high current is typically required in order to generate a sufficient temperature to activate such antifulse elements. Further, due to the high rate at which many conventional metal contacts dissipate heat, such contacts may necessitate the input of even greater amounts of current in order to adequately heat and activate an antifuse element. Moreover, the typical use of conventional, relatively large metal contacts on such EEPROMs is somewhat undesirable from the standpoint that such contacts consume a great deal of surface area or xe2x80x9creal estatexe2x80x9d on the surface of the semiconductor device. Thus, conventional metal contacts limit the density of active device regions on the semiconductor device.
The dissipation of heat away from the memory cell through the metal contact is especially undesirable when the memory cell includes a phase change component, such as a chalcogenide material layer, such as the EEPROM devices disclosed in U.S. Pat. No. 5,789,758 (hereinafter xe2x80x9cthe ""758 patentxe2x80x9d), which issued to Alan R. Reinberg on Aug. 4, 1998. As is known in the art, chalcogenide materials and some other phase change materials exhibit different electrical characteristics, depending upon their state. For example, chalcogenide materials have a lower electrical conductivity in their amorphous state, or phase, than in their crystalline state. Chalcogenide materials may be changed from an amorphous state to a crystalline state by increasing their temperature. The electrical conductivity of the material may vary incrementally between the amorphous state and the crystalline state.
Some EEPROMs include metal contacts that are offset from the active device regions of the former. Such offset contacts are said to reduce the dissipation of thermal energy from the active device regions. Although the direct dissipation of heat from the active device regions of such EEPROM structures may be reduced, thermal energy is conducted to the offset metal contacts, which dissipate heat at approximately the same rate as conventionally positioned metal contacts.
Thus, an electrical and thermal contact is needed which facilitates the input of reduced current and voltage into a structure that is electrically contacted thereto (i.e., conserves energy) and which has a low rate of thermal dissipation relative to conventional metal contacts. A more compact electrical and/or thermal contact structure is also needed.
The electrical and thermal contact of the present invention addresses each of the foregoing needs. The electrical and thermal contact of the present invention contacts a structure of a semiconductor device, such as a phase change component of an active device region thereof, as disclosed in the ""758 patent, and in U.S. Pat. No. 5,789,277 (xe2x80x9cthe ""277 patentxe2x80x9d), which issued to Zahorik et al. on Aug. 4, 1998, the disclosures of both of which are hereby incorporated by reference in their entirety. The electrical and thermal contact of the present invention includes an intermediate conductive layer adjacent the contacted structure, a thermal insulator component, which is also referred to as an insulator component, that is adjacent the intermediate conductive layer, and a contact layer that is adjacent the thermal insulator component and which partially contacts the intermediate conductive layer. Preferably, the contact layer and intermediate conductive layer are in electrical and thermal communication with the contacted structure. The thermal insulator component is preferably sandwiched between the intermediate conductive layer and the contact layer, such that the thermal insulator component is substantially enveloped by the intermediate conductive and contact layers. An exemplary active device region to which the electrical and thermal contact of the present invention may be contacted is a memory cell, or element, of an electrically erasable programmable memory (EEPROM) device.
Fabricating the electrical and thermal contact includes forming a dielectric layer around the lateral peripheral portions of a semiconductor device structure to be contacted, patterning the dielectric layer to expose at least a portion of the semiconductor device structure to be contacted, such as an active device region thereof, depositing a first thin conductive layer, depositing another dielectric layer adjacent the first thin conductive layer, patterning the dielectric layer to define a thermal insulator component, depositing a second thin conductive layer adjacent the thermal insulator component and in electrical communication with the first thin conductive layer, and patterning the first and second thin conductive layers to define the intermediate conductive layer and the contact layer, respectively. The dielectric layer is fabricated from an electrically and thermally conductive material. Preferably, during patterning of the dielectric layer, the first thin conductive layer is utilized as an etch stop. The processes that may be employed to fabricate the electrical and thermal contact facilitate the fabrication of a relatively small electrical and thermal contact, when compared with conventional metal contacts.
Other advantages of the present invention will become apparent to those of ordinary skill in the relevant art through a consideration of the ensuing description, the accompanying drawings, and the appended claims.